1. Field of the Invention
The present invention relates to a thyristor-based semiconductor device and a method for manufacturing the semiconductor device.
2. Description of the Related Art
As shown in FIG. 15A, in a general thyristor-based semiconductor device, four layers of p-type regions (hereinafter, p-regions) p1 and p2 and n-type regions (hereinafter, n-regions) n1 and n2 are formed in such a manner that the p- and n-regions are in turn arranged to construct a p1/n1/p2/n2 structure. Furthermore, an anode electrode A is connected to the p-region p1 at one outermost end, while a cathode electrode K is connected to the n-region n2 at the other outermost end. Moreover, a gate electrode G is connected to the p-region p2 in an intermediate area. As the structures of such a thyristor, there are a vertical p1/n1/p2/n2 structure formed in a surface layer of a silicon substrate, and a horizontal p1/n1/p2/n2 structure formed by use of an SOI substrate.
In the semiconductor device with the above-described structure, as shown in FIG. 15B, upon application of a forward bias between the anode and cathode electrodes A and K, holes are supplied from the p-region p1 connected to the anode electrode A into the n-region n1, while electrons are supplied from the n-region n2 connected to the cathode electrode K into the p-region p2. These holes and electrons are recombined at the pn junction between the n-region n1 and the p-region p2, which leads to current flow, and thus the thyristor enters the on-state.
In contrast, applying a reverse bias between the anode and cathode electrodes A and K allows the thyristor to enter the off-state as shown in FIG. 15C. However, if merely a reverse bias is applied, it takes a time period as long as several milliseconds for the thyristor to enter the substantial off-state. Specifically, if the thyristor has entered the on-state, merely applying a reverse bias between the anode and cathode electrodes A and K does not drive the thyristor to spontaneously enter the off-state. In order for the thyristor to enter the off-state, there is a need that all excess carriers flowing in the n-region n1 and the p-region p2 be swept out of these regions or be recombined, by decreasing the current to below the holding current or turning power off.
Therefore, in order to switch the thyristor from the on-state to the off-state, in addition to application of a reverse bias between the anode and cathode electrodes A and K, application of voltage to the gate electrode provided over the p-region p2 is implemented. This voltage application provides an operation in which an electric field is generated in the p-region p2 and thus electrons as the excess carriers are forcibly discharged, so that the thyristor enters the substantial off-state more rapidly.
FIG. 16 shows the relationship, in the semiconductor device with the above-described structure, between the voltage (VAK) between the anode and cathode electrodes A and K and the current (I) flowing through this semiconductor device. As shown in FIG. 16, when the level of positive voltage applied to the anode A is increased and thus the voltage (VAK) reaches the critical voltage (VFB), the pn junction between the n-region n1 and the p-region p2 is forward biased. At this time, the voltage (VAK) decreases and a current larger than the holding current (IH) becomes to flow. In contrast, when the voltage (VAK) is lower than the critical voltage (VFB), the switching current (IS) smaller than the holding current (IH) flows. It is not until the voltage (VAK) surpasses the critical voltage (VFB) that a current larger than the holding current (IH) flows.
In order to further increase the speed of the above-described switching operation, proposals are made to provide a gate electrode based on a MOS structure in which an electrode film is formed over the p-region p2 with the intermediary of an insulating film therebetween. (The following documents are examples of the proposals: U.S. Pat. No. 6,462,359 B1; F. Nemati and J. Plummer, 1998, VLSI Tech., pp. 66; F. Nemati and J. Plummer, 1999, IEDM Tech., pp. 283; and F. Nemati et. al., 2004, IEDM Tech., pp. 273).